The object of the tender is an an electroplating tool (later also “Equipment”), which can electroplate metallic copper films for use as electrically conducting lines and vias onto 150- and 200 mm silicon wafers typical of the semiconductor industry.

The reference price ("the total price") will consist of the price for the equipment in required minimum configuration described in Annex 1. The optional features are not included in the total price of the equipment.

The object of the tender process is described in more detail in the invitation to tender documents.

VTT is looking for a single electroplating tool (or "equipment") which can electroplate metallic copper and UBM layers for use as electrically conducting lines and vias onto 150- and 200 mm silicon wafers typical of the semiconductor industry. The tool will be installed to the Micronova backend cleanroom. The tool must feature automated execution of recipes and computer controlled automation and datalogging. Wafer handling must be automatic from a 25 wafer cassette (*).

The tool should also have provisions for manually loading wafers to the plating chambers thus allowing nonstandard wafers to be processed. Multiple baths are required: two plating baths must be provided for three Cu-based plating processes (expecting there to be some overlap) and four baths for UBM metal baths for Ni, Sn, SnAg alloy, and indium.

The three Cu-based applications are:

1) Cu-fill TSV (through-silicon-via) with aspect ratio up to 10:1 (10 um diameter and 100 um deep) plated from a conformal Ru or PVD Cu seed,

2) Cu-bump or pillar plating through resist using Cu seed layers, and

3) Damascene RDL plating of ~1 um Cu in etched damascene trenches and vias, also using Ru seed layers.

For the Cu-TSV bath, a membrane within the electroplating cell is required to separate additives from the Cu-anode and thus improve the control and lifetime of the electroplating additives. In addition, the vendor must supply a Vacuum Prewetting chamber to enable wetting of etched TSV with electrolyte before filling, and must be able to demonstrate void-free bottom-up filling of the vias.

Knowledge regarding TSV-fill applications is essential for the tooling to be accepted. Recipe editing and execution using computer control of wafer handling, wafer flow, power supplies, additive management, datalog collection and so on as is typical of the semiconductor industry.

(*) Note that the term ”automatic handling” is reserved for tools which take wafers directly from a standard semiconductor wafer cassette and then return them to the same or similiar cassette (”dry-in, dry-out”).